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INTEGRATED CIRCUITS
DATA SHEET
TEA6320 Sound fader control circuit
Preliminary specification Supersedes data of September 1992 File under Integrated Circuits, IC01 1995 Dec 19
Philips Semiconductors
Preliminary specification
Sound fader control circuit
FEATURES * Source selector for four stereo and one mono inputs * Interface for noise reduction circuits * Interface for external equalizer * Volume, balance and fader control * Special loudness characteristic automatically controlled in combination with volume setting * Bass and treble control * Mute control at audio signal zero crossing * Fast mute control via I2C-bus * Fast mute control via pin * I2C-bus control for all functions * Power supply with internal power-on reset. QUICK REFERENCE DATA SYMBOL VCC ICC Vo(rms) Gv Gstep(vol) Gbass Gtreble Gstep(treble) (S+N)/N RR100 cs PARAMETER supply voltage supply current maximum output voltage level voltage gain step resolution (volume) bass control treble control step resolution (bass, treble) signal-plus-noise to noise ratio ripple rejection channel separation VO = 2.0 V; Gv = 0 dB; unweighted Vr(rms) < 200 mV; f = 100 Hz; Gv = 0 dB 250 Hz f 10 kHz; Gv = 0 dB VCC = 8.5 V VCC = 8.5 V; THD 0.1% CONDITIONS MIN. 7.5 - - -86 - -15 -12 - - - 90 TYP. 8.5 26 2000 - 1 - - 1.5 105 76 96 GENERAL DESCRIPTION
TEA6320
The sound fader control circuit TEA6320 is an I2C-bus controlled stereo preamplifier for car radio hi-fi sound applications.
MAX. 9.5 - - +20 - +15 +12 - - - -
UNIT V mA mV dB dB dB dB dB dB dB dB
ORDERING INFORMATION TYPE NUMBER TEA6320 TEA6320T PACKAGE NAME SDIP32 SO32 DESCRIPTION plastic shrink dual in-line package; 32 leads (400 mil) plastic small outline package; 32 leads; body width 7.5 mm VERSION SOT232-1 SOT287-1
1995 Dec 19
2
8.2 nF 20 k 2.2 k
handbook, full pagewidth
1995 Dec 19
8.2 nF 20 k CKVL 220 nF 100 F Vref 10 21 8 VCC 31 POWER SUPPLY GND 47 F 19 9 x 220 nF 16 input left source 15 13 11 SOURCE input mono source 14 SELECTOR 2
BLOCK DIAGRAM
Philips Semiconductors
Sound fader control circuit
2.2 k 33 nF 5.6 nF 150 nF Cm 10 nF MUTE
9
7
6
5
12 MUTE FUNCTION ZERO CROSS DETECTOR VOLUME II 0 to -55 dB BALANCE FADER REAR
3
VOLUME I +20 to -31 dB LOUDNESS LEFT
BASS LEFT 15 dB
TREBLE LEFT 12 dB
output left VOLUME II 0 to -55 dB BALANCE FADER FRONT 4
32 LOGIC I2C-BUS RECEIVER 1
SCL SDA
3
input right source CKIN
22 20 18 17 23 25
VOLUME I +20 to -31 dB LOUDNESS RIGHT
BASS RIGHT 15 dB
TREBLE RIGHT 12 dB
VOLUME II 0 to -55 dB BALANCE FADER FRONT
29
output right VOLUME II 0 to -55 dB BALANCE FADER REAR 30
TEA6320
24 26 27 28
MED421
CKVL 220 nF
Preliminary specification
150 nF 5.6 nF 33 nF
TEA6320
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Sound fader control circuit
PINNING SYMBOL PIN SDA GND OUTLR OUTLF TL B2L B1L IVL ILL QSL IDL MUTE ICL IMO IBL IAL IAR IBR CAP ICR Vref IDR QSR ILR IVR B1R B2R TR OUTRF OUTRR VCC SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ground output left rear output left front treble control capacitor left channel or input from an external equalizer bass control capacitor left channel or output to an external equalizer bass control capacitor, left channel input volume I, left control part input loudness, left control part output source selector, left channel input D left source mute control input C left source input mono source input B left source input A left source input A right source input B right source electronic filtering for supply input C right source reference voltage (0.5VCC) input D right source output source selector right channel input loudness right channel input volume I, right control part bass control capacitor right channel bass control capacitor right channel or output to an external equalizer treble control capacitor right channel or input from an external equalizer output right front output right rear supply voltage serial clock input Fig.2 Pin configuration.
IBL 15 IAL 16
MED422
TEA6320
DESCRIPTION serial data input/output
handbook, halfpage
SDA GND OUTLR OUTLF TL B2L B1L IVL ILL
1 2 3 4 5 6 7 8
32 SCL 31 VCC 30 OUTRR 29 OUTRF 28 TR 27 B2R 26 B1R 25 IVR
TEA6320
9 24 ILR 23 QSR 22 IDR 21 Vref 20 ICR 19 CAP 18 IBR 17 IAR QSL 10 IDL 11 MUTE 12 ICL 13 IMO 14
1995 Dec 19
4
Philips Semiconductors
Preliminary specification
Sound fader control circuit
FUNCTIONAL DESCRIPTION The source selector selects one of 4 stereo inputs or the mono input. The maximum input signal voltage is Vi(rms) = 2 V. The outputs of the source selector and the inputs of the following volume control parts are available at pins 8 and 10 for the left channel and pins 23 and 25 for the right channel. This offers the possibility of interfacing a noise reduction system. The volume control function is split into two sections: volume I control block and volume II control block. The control range of volume I is between +20 dB and -31 dB in steps of 1 dB. The volume II control range is between 0 dB and -55 dB in steps of 1 dB. Although the theoretical possible control range is 106 dB (+20 to -86 dB), in practice a range of 86 dB (+20 to -66 dB) is recommended. The gain/attenuation setting of the volume I control block is common for both channels. The volume I control block operates in combination with the loudness control. The filter is linear when the maximum gain for the volume I control (+20 dB) is selected. The filter characteristic increases automatically over a range of 32 dB down to a setting of -12 dB. That means the maximum filter characteristic is obtained at -12 dB setting of volume I. Further reduction of the volume does not further influence the filter characteristic (see Fig.5). The maximum selected filter characteristic is determined by external components. The proposed application gives a maximum boost of 17 dB for bass and 4.5 dB for treble. The loudness may be switched on or off via I2C-bus control (see Table 7). The volume I control block is followed by the bass control block. A single external capacitor of 33 nF for each channel in combination with internal resistors, provides the frequency response of the bass control (see Fig.3). The adjustable range is between -15 and +15 dB at 40 Hz. Both loudness and bass control result in a maximum bass boost of 32 dB for low volume settings. The treble control block offers a control range between -12 and +12 dB in steps of 1.5 dB at 15 kHz. The filter characteristic is determined by a single capacitor of 5.6 nF for each channel in combination with internal resistors (see Fig.4). The basic step width of bass and treble control is 3 dB. The intermediate steps are obtained by switching 1.5 dB boost and 1.5 dB attenuation steps. The bass and treble control functions can be switched off via I2C-bus. In this event the internal signal flow is disconnected. The connections B2L and B2R are outputs 1995 Dec 19 5
TEA6320
and TL and TR are inputs for inserting an external equalizer. The last section of the circuit is the volume II block. The balance and fader functions are performed using the same control blocks. This is realized by 4 independently controllable attenuators, one for each output. The control range of these attenuators is 55 dB in steps of 1 dB with an additional mute step. The circuit provides 3 mute modes: 1. Zero crossing mode mute via I2C-bus using 2 independent zero crossing detectors (ZCM, see Tables 2 and 9 and Fig.16). 2. Fast mute via MUTE pin (see Fig.10). 3. Fast mute via I2C-bus either by general mute (GMU, see Tables 2 and 9) or volume II block setting (see Table 4). The mute function is performed immediately if ZCM is cleared (ZCM = 0). If the bit is set (ZCM = 1) the mute is activated after changing the GMU bit. The actual mute switching is delayed until the next zero crossing of the audio frequency signal. As the two audio channels (left and right) are independent, two comparators are built-in to control independent mute switches. To avoid a large delay of mute switching when very low frequencies are processed, the maximum delay time is limited to typically 100 ms by an integrated timing circuit and an external capacitor (Cm = 10 nF, see Fig.10). This timing circuit is triggered by reception of a new data word for the switch function which includes the GMU bit. After a discharge and charge period of an external capacitor the muting switch follows the GMU bit if no zero crossing was detected during that time. The mute function can also be controlled externally. If the mute pin is switched to ground all outputs are muted immediately (hardware mute). This mute request overwrites all mute controls via the I2C-bus for the time the pin is held LOW. The hardware mute position is not stored in the TEA6320. For the turn on/off behaviour the following explanation is generally valid. To avoid AF output caused by the input signal coming from preceding stages, which produces output during drop of VCC, the mute has to be set, before the VCC will drop. This can be achieved by I2C-bus control or by grounding the MUTE pin. For use where is no mute in the application before turn off, a supply voltage drop of more than 1 x VBE will result in a mute during the voltage drop.
Philips Semiconductors
Preliminary specification
Sound fader control circuit
The power supply should include a VCC buffer capacitor, which provides a discharging time constant. If the input signal does not disappear after turn off the input will become audible after certain time. A 4.7 k resistor discharges the VCC buffer capacitor, because the internal current of the IC does not discharge it completely.
TEA6320
The hardware mute function is favourable for use in Radio Data System (RDS) applications. The zero crossing mute avoids modulation plops. This feature is an advantage for mute during changing presets and/or sources (e.g. traffic announcement during cassette playback).
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCC Vn Tamb Tstg Ves Note 1. Human body model: C = 100 pF; R = 1.5 k; V 2 kV. Charge device model: C = 200 pF; R = 0 ; V 500 V. PARAMETER supply voltage voltage at all pins except pin 2 referenced to GND (pin 2) operating ambient temperature storage temperature electrostatic handling note 1 CONDITIONS 0 0 -40 -65 MIN. MAX. 10 VCC +85 +150 V V C C UNIT
1995 Dec 19
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Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
CHARACTERISTICS VCC = 8.5 V; RS = 600 ; RL = 10 k; CL = 2.5 nF; AC coupled; f = 1 kHz; Tamb = 25 C; gain control Gv = 0 dB; bass linear; treble linear; fader off; balance in mid position; loudness off; unless otherwise specified. SYMBOL VCC ICC VDC Vref Gv(max) Vo(rms) PARAMETER supply voltage supply current internal DC voltage at inputs and outputs internal reference voltage at pin 21 maximum voltage gain output voltage level for Pmax at the power output stage start of clipping THD 0.5%; see Fig.11 THD = 1% RL = 2 k; CL = 10 nF; THD = 1% Vi(rms) fro input sensitivity roll-off frequency Vo = 2000 mV; Gv = 20 dB CKIN = 220 nF; CKVL = 220 nF; Zi = Zi(min) low frequency (-1 dB) low frequency (-3 dB) high frequency (-1 dB) CKIN = 470 nF; CKVL = 100 nF; Zi = Zi(typ) low frequency (-3 dB) cs THD channel separation total harmonic distortion Vi = 2 V; frequency range 250 Hz to 10 kHz frequency range 20 Hz to 12.5 kHz Vi = 100 mV; Gv = 20 dB Vi = 1 V; Gv = 0 dB Vi = 2 V; Gv = 0 dB Vi = 2 V; Gv = -10 dB RR ripple rejection Vr(rms) < 200 mV f = 100 Hz f = 40 Hz to 12.5 kHz (S+N)/N signal-plus-noise to noise ratio unweighted; 20 Hz to 20 kHz (RMS); Vo = 2.0 V; see Figs 6 and 7 CCIR468-2 weighted; quasi peak; Vo = 2.0 V Gv = 0 dB Gv = 12 dB Gv = 20 dB - - - 95 88 81 - - - dB dB dB 70 - - 76 66 105 - - - dB dB dB - - - - 0.1 0.05 0.1 0.1 - 0.15 - - % % % % 60 30 17 - - - - - - - Hz Hz Hz Hz - 2300 2000 - 2000 - - 200 - - - - mV mV mV mV RS = 0 ; RL = CONDITIONS MIN. 7.5 - 3.83 - 19 TYP. 8.5 26 4.25 4.25 20 MAX. 9.5 33 4.68 - 21 UNIT V mA V V dB
20000 -
90
96
-
dB
1995 Dec 19
7
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
SYMBOL Pno(rms)
PARAMETER noise output power (RMS value) only contribution of TEA6320; power amplifier for 6 W crosstalk V bus ( p - p ) 20 log -------------------------- between bus V o ( rms ) inputs and signal outputs
CONDITIONS mute position; note 1
MIN. -
TYP. -
MAX. 10
UNIT nW
ct
note 2
-
110
-
dB
Source selector Zi S Vi(rms) Voffset input impedance input isolation of one selected source to any other input maximum input voltage (RMS value) DC offset voltage at source selector output by selection of any inputs output impedance output load resistance output load capacity voltage gain, source selector f = 1 kHz f = 12.5 kHz THD < 0.5%; VCC = 8.5 V THD < 0.5%; VCC = 7.5 V 25 - - - - - 35 105 95 2.15 1.8 - 45 - - - - 10 k dB dB V V mV
Zo RL CL Gv Zi Zo RL CL RDCL Vi(rms) Vno
- 10 0 -
80 - - 0
120 - 2500 -
k pF dB
Control part (source selector disconnected; source resistance 600 ) input impedance volume input input impedance loudness input output impedance output load resistance output load capacity DC load resistance at output to ground maximum input voltage (RMS value) noise output voltage THD < 0.5% CCIR468-2 weighted; quasi peak Gv = 20 dB Gv = 0 dB Gv = -66 dB mute position CRtot Gstep total continuous control range recommended control range step resolution step error between any adjoining step - - - - - - - - 110 33 13 10 106 86 1 - 220 50 22 - - - - 0.5 V V V V dB dB dB dB 100 25 - 2 0 4.7 - 150 33 80 - - - 2.15 200 40 120 - 10 - - k k k nF k V
1995 Dec 19
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Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
SYMBOL Ga Gt MUTEatt Voffset
PARAMETER attenuator set error gain tracking error mute attenuation DC step offset between any adjoining step
CONDITIONS Gv = +20 to -50 dB Gv = -51 to -66 dB Gv = +20 to -50 dB see Fig.10 Gv = 0 to -66 dB Gv = 20 to 0 dB
MIN. - - - 100 - - -
TYP. - - - 110 0.2 2 -
MAX. 2 3 2 - 10 15 10
UNIT dB dB dB dB mV mV mV
DC step offset between any step to Gv = 0 to -66 dB mute Volume I control and loudness CRvol Gv Gstep LBmax continuous volume control range voltage gain step resolution maximum loudness boost loudness on; referred to loudness off; boost is determined by external components f = 40 Hz f = 10 kHz Bass control Gbass Gstep bass control, maximum boost maximum attenuation step resolution (toggle switching) step error between any adjoining step Voffset Treble control Gtreble treble control, maximum boost maximum attenuation maximum boost Gstep step resolution (toggle switching) step error between any adjoining step Voffset DC step offset in any treble position f = 15 kHz f = 15 kHz f > 15 kHz f = 15 kHz f = 15 kHz DC step offset in any bass position f = 40 Hz f = 40 Hz f = 40 Hz f = 40 Hz
- -31 -
51 - 1
- +20 -
dB dB dB
- -
17 4.5
- -
dB dB
14 14 - - -
15 15 1.5 - -
16 16 - 0.5 20
dB dB dB dB mV
11 11 - - - -
12 12 - 1.5 - -
13 13 15 - 0.5 10
dB dB dB dB dB mV
Volume II, balance and fader control CR Gstep continuous attenuation fader and volume control range step resolution attenuation set error 53.5 - - 55 1 - 56.5 2 1.5 dB dB dB
1995 Dec 19
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Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Mute function (see Fig.10) HARDWARE MUTE Vsw mute switch level (2 x VBE) input level input current VswLOW = 1 V - - -300 - - 0.3 -300 - Cm = 10 nF - - 1.45 - - - - 0.6 -150 2.2 100 30 - 1.0 - VCC 0.5 V
mute active
VswLOW Ii VswHIGH td(mute) Id Ich VswDEL td Vwind V A V ms A A V ms mV
mute passive: level internally defined
saturation voltage delay until mute passive
ZERO CROSSING MUTE discharge current charge current delay switch level (3 x VBE) delay time window for audio signal zero crossing detection 1.2 - - - 40
Muting at power supply drop VCCdrop supply drop for mute active - V19 - 0.7 - V
Power-on reset (when reset is active the GMU-bit (general mute) is set and the I2C-bus receiver is in reset position) VCC increasing supply voltage start of reset end of reset decreasing supply voltage start of reset Digital part (I2C-bus pins); note 3 ViH ViL IiH IiL VoL HIGH level input voltage LOW level input voltage HIGH level input current LOW level input current LOW level output voltage IL = 3 mA 3 -0.3 -10 -10 - - - - - - 9.5 +1.5 +10 +10 0.4 V V A A V - 5.2 4.2 - 6.5 5.5 2.5 7.2 6.2 V V V
Notes to the characteristics 1. The indicated values for output power assume a 6 W power amplifier at 4 with 20 dB gain and a fixed attenuator of 12 dB in front of it. Signal-to-noise ratios exclude noise contribution of the power amplifier. 2. The transmission contains: total initialization with MAD and subaddress for volume and 8 data words, see also definition of characteristics, clock frequency = 50 kHz, repetition burst rate = 400 Hz, maximum bus signal amplitude = 5 V (p-p). 3. The AC characteristics are in accordance with the I2C-bus specification. This specification, "The I2C-bus and how to use it", can be ordered using the code 9398 393 40011. 1995 Dec 19 10
Philips Semiconductors
Preliminary specification
Sound fader control circuit
I2C-BUS PROTOCOL I2C-bus format S(1) Notes 1. S = START condition. 2. SLAVE ADDRESS (MAD) = 1000 0000. 3. A = acknowledge, generated by the slave. 4. SUBADDRESS (SAD), see Table 1. SLAVE ADDRESS(2) A(3) SUBADDRESS(4) A(3) DATA(5)
TEA6320
A(3)
P(6)
5. DATA, see Table 1; if more than 1 byte of DATA is transmitted, then auto-increment of the significant subaddress is performed. 6. P = STOP condition. Table 1 Second byte after MAD MSB FUNCTION Volume/loudness Fader front right Fader front left Fader rear right Fader rear left Bass Treble Switch Note 1. Significant subaddress. V FFR FFL FRR FRL BA TR S BIT 7 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 2(1) 0 0 0 0 1 1 1 1 1(1) 0 0 1 1 0 0 1 1 LSB 0(1) 0 1 0 1 0 1 0 1
1995 Dec 19
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Philips Semiconductors
Preliminary specification
Sound fader control circuit
Table 2 Definition of third byte after MAD and SAD MSB FUNCTION Volume/loudness Fader front right Fader front left Fader rear right Fader rear left Bass Treble Switch Notes 1. Zero crossing mode. 2. Switch loudness on/off. 3. Volume control. 4. Don't care bits (logic 1 during testing). 5. Fader control front right. 6. Fader control front left. 7. Fader control rear right. 8. Fader control rear left. 9. Bass control. 10. Treble control. 11. Mute control for all outputs (general mute). 12. Source selector control. V FFR FFL FRR FRL BA TR S BIT 7 ZCM(1) X(4) X(4) X(4) X(4) X(4) X(4) GMU(11) 6 LOFF(2) X(4) X(4) X(4) X(4) X(4) X(4) X(4) 5 V5(3) FFL5(6) FRR5(7) FRL5(8) X(4) X(4) X(4) 4 V4(3) FFL4(6) FRR4(7) FRL4(8) BA4(9) TR4(10) X(4) 3 V3(3) FFL3(6) FRR3(7) FRL3(8) BA3(9) TR3(10) X(4) 2 V2(3) FFL2(6) FRR2(7) FRL2(8) BA2(9) TR2(10) SC2(12)
TEA6320
LSB 1 V1(3) FFL1(6) FRR1(7) FRL1(8) BA1(9) TR1(10) SC1(12) 0 V0(3) FFL0(6) FRR0(7) FRL0(8) BA0(9) TR0(10) SC0(12)
FFR5(5) FFR4(5) FFR3(5) FFR2(5) FFR1(5) FFR0(5)
1995 Dec 19
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Philips Semiconductors
Preliminary specification
Sound fader control circuit
Table 3 Volume I setting Gv (dB) DATA V5 V4 V3 V2 V1
TEA6320
V0
Loudness on: the increment of the loudness characteristics is linear at every volume step in the range from +20 to -11 dB +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
1995 Dec 19
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Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
Gv (dB)
DATA V5 V4 V3 V2 V1 V0
Loudness characteristic is constant in a range from -11 dB to -31 dB -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 -22 -23 -24 -25 -26 -27 -28 -29 -30 -31 -28 -29 -30 -31 -28 -29 -30 -31 -28 -29 -30 -31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Repetition of steps in a range from -28 dB to -31 dB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0
1995 Dec 19
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Philips Semiconductors
Preliminary specification
Sound fader control circuit
Table 4 Volume II setting (fader and balance); note 1 DATA FRR5 Gv (dB) FRL5 FFL5 FFR5 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 -22 -23 -24 -25 -26 -27 -28 -29 -30 -31 -32 -33 -34 1995 Dec 19 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 FRR4 FRL4 FFL4 FFR4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 15 FRR3 FRL3 FFL3 FFR3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 FRR2 FRL2 FFL2 FFR2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 FRR1 FRL1 FFL1 FFR1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
TEA6320
FRR0 FRL0 FFL0 FFR0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
DATA FRR5 Gv (dB) FRL5 FFL5 FFR5 -35 -36 -37 -38 -39 -40 -41 -42 -43 -44 -45 -46 -47 -48 -49 -50 -51 -52 -53 -54 -55 mute mute mute mute mute mute mute mute Note 1. For a particular range the data is always the same, only the subaddress changes. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRR4 FRL4 FFL4 FFR4 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRR3 FRL3 FFL3 FFR3 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 FRR2 FRL2 FFL2 FFR2 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 FRR1 FRL1 FFL1 FFR1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 FRR0 FRL0 FFL0 FFR0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
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Philips Semiconductors
Preliminary specification
Sound fader control circuit
Table 5 Bass setting Gbass (dB) +15.0 +13.5 +15.0 +13.5 +15.0 +13.5 +12.0 +10.5 +9.0 +7.5 +6.0 +4.5 +3.0 +1.5 0(1) 0(2) -1.5 -3.0 -4.5 -6.0 -7.5 -9.0 -10.5 -12.0 -13.5 -15.0 -13.5 -15.0 note 3 note 3 note 3 notes 3 and 4 Notes 1. Recommended data word for step 0 dB. 2. Result of 1.5 dB boost and 1.5 dB attenuation. 3. The last four bass control data words mute the bass response. DATA BA4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BA3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 BA2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 BA1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
TEA6320
BA0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
4. The last bass control and treble control data words (00000) enable the external equalizer connection.
1995 Dec 19
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Philips Semiconductors
Preliminary specification
Sound fader control circuit
Table 6 Treble setting Gtreble (dB) +12.0 +10.5 +12.0 +10.5 +12.0 +10.5 +12.0 +10.5 +9.0 +7.5 +6.0 +4.5 +3.0 +1.5 0(1) 0(2) -1.5 -3.0 -4.5 -6.0 -7.5 -9.0 -10.5 -12.0 note 3 note 3 note 3 note 3 note 3 note 3 note 3 notes 3 and 4 Notes 1. Recommended data word for step 0 dB. 2. Result of 1.5 dB boost and 1.5 dB attenuation. 3. The last eight treble control data words select treble output. DATA TR4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TR3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 TR2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 TR1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
TEA6320
TR0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
4. The last treble control and bass control data words (00000) enable the external equalizer connection.
1995 Dec 19
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Philips Semiconductors
Preliminary specification
Sound fader control circuit
Table 7 Loudness setting DATA LOFF 0 1 Selected input DATA FUNCTION SC2 Stereo inputs IAL and IAR Stereo inputs IBL and IBR Stereo inputs ICL and ICR Stereo inputs IDL and IDR Mono input IMO Note 1. X = don't care bits (logic 1 during testing). 1 1 1 1 0 SC1 1 1 0 0 X(1) SC0 1 0 1 0 X(1) FUNCTION Table 9 Mute mode
TEA6320
CHARACTERISTIC With loudness Linear Table 8
DATA GMU Direct mute off Mute off delayed until the next zero crossing Direct mute Mute delayed until the next zero crossing 0 0 1 1 ZCM 0 1 0 1
1995 Dec 19
19
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
handbook, full pagewidth
18
MED423
Gbass (dB)
12
6
0
-6
-12
-18 10
10 2
10 3
f (Hz)
10 4
Fig.3 Bass control.
handbook, full pagewidth
15
MED424
Gtreble (dB)
10
5
0
-5
-10
-15 10 2
10 3
10 4
f (Hz)
10 5
Fig.4 Treble control.
1995 Dec 19
20
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
MED425
handbook,20 pagewidth full
Gv (dB) 10
0
-10
-20
-30
-40 10
10 2
10 3
10 4
f (Hz)
10 5
Fig.5 Volume control with loudness (including low roll-off frequency).
MED426
handbook, full pagewidth
100
S/N (dB) 90
(1)
(2) (3)
80
70
60
50 10 -4 (1) Vi = 2.0 V. (2) Vi = 0.5 V. (3) Vi = 0.2 V.
10 -3
10 -2
10 -1
1
Po (W)
10
Fig.6 Signal-to-noise ratio; noise weighted: CCIR468-2, quasi peak.
1995 Dec 19
21
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
MED427
handbook, full pagewidth
110
S/N (dB)
(1)
100
(2)
90
(3)
80
70
60 10 -4 (1) Unweighted RMS. (2) CCIR468-2 RMS. (3) CCIR468-2 quasi peak.
10 -3
10 -2
10 -1
1
Po (W)
10
Fig.7 Signal-to-noise ratio; Vi = 2 V; Pmax = 6 W.
handbook, full pagewidth
200
MED428
noise (V) 150
100
(1)
50
(2)
0 -70 Stereo/mono inputs. (1) Loudness on. (2) Loudness off.
-50
-30
-10
10
gain (dB)
30
Fig.8 Noise output voltage; CCIR468-2, quasi peak.
1995 Dec 19
22
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
handbook, full pagewidth
-60
MED429
(dB)
-80
-100
-120
-140
20
50
10 2
200
500
10 3
2 x 10 3
5 x 10 3
10 4
2 x 10 4 f (Hz)
Fig.9 Muting.
1995 Dec 19
23
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
handbook, full pagewidth
mute pin 12
hardware mute switch ICH = -150 A
TEA6320
ID = 0.6 A
Cm = 10 nF
U (V) VCC 8.5
0.5 ms delay until mute passive
I (A)
0
delay switch (1) 2.2 level mute switch 1.45 level
-150
MED430
100 ms zero crossing mute start end of delay hard mute on hard mute off
t (ms)
(1) Typically 2.2 V; referenced to 3 x VBE.
Fig.10 Mute function diagram.
1995 Dec 19
24
Philips Semiconductors
Preliminary specification
Sound fader control circuit
If the 20 dB gain is not required for the maximum volume position, it will be an advantage to use the maximum boost gain and then increased attenuation in the last section, Volume II.
TEA6320
Therefore the loudness will be at the correct place and a lower noise and offset voltage will be achieved.
handbook, halfpage
POWER STAGE
TEA6320
G = 20 dB VI(min) = 200 mV P(max) = 100 W at 4
MBE899
Vo = 2 V for P(max)
a.
handbook, halfpage
POWER STAGE
TEA6320
G = 26 dB VI(min) = 200 mV P(max) = 100 W at 4
MED431
Vo = 1 V for P(max)
b.
a. Gain volume I = 20 dB (Gv(max)); gain volume II = 0 dB; fader and balance range = 55 dB. b. Gain volume I = 20 dB (Gv(max)); gain volume II = -6 dB global setting; fader and balance range now 49 dB, previously 55 dB.
Fig.11 Level diagram.
1995 Dec 19
25
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
handbook, full pagewidth
+
VP VCC 8.5 V inputs
16 15 13 11 14 17 18 20 22 31 3 4
+8.5 V to oscilloscope
4.7 k
470 F
TEA6320
29 30
outputs to oscilloscope
2
19
21
4 x 4.7 F
9 x 220 nF 9 x 600
47 F
100 F
4 x 10 k
MED432
Fig.12 Turn-on/off power supply circuit diagram.
handbook, full pagewidth
10
MED433
(V) 8
(1) 6
4 (2)
2
0 0 (1) VCC. (2) VO. 1 2 3 4 t (s) 5
Fig.13 Turn-on/off behaviour.
1995 Dec 19
26
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
handbook, full pagewidth
220 nF 100 F 21 10 VCC = 8.5 V 0.1 F 10 k 1000 F 19 VP 0.2 V (RMS) 47 F 31 8
33 nF
5.6 nF 5 12
10 nF
7
6
32 2 TEA6320 1
SCL
SDA
600 220 nF
input A to D left and right and input mono
output right output left front and rear
4.7 F VO
23
25
26
27
28
MED434
220 nF
33 nF
5.6 nF
Fig.14 Test circuit for power supply ripple rejection (RR).
handbook, full pagewidth
220 nF 100 F 21 10 VCC = 8.5 V 470 F Vp 47 F 0.1 F 2 31 8
33 nF
5.6 nF 5 12
10 nF
7
6
32 TEA6320 19
SCL
1
SDA
input A to D right and left 220 nF Vi 600 220 nF input A to D left and right and input mono output left output right front and rear 4.7 F VO
23
25
26
27
28 5.6 nF
MED435
220 nF
33 nF
Fig.15 Test circuit for channel separation (cs). 1995 Dec 19 27
Philips Semiconductors
Preliminary specification
Sound fader control circuit
Selection of input signals by using the zero crossing mute mode A selection from input A (IAL) to input B (IBL) left sources produces a modulation click depending on the difference of the signal values at the time of switching. At t1 the maximum possible difference between signals is 7 V(p-p) (see Fig. 16) and gives a large click. Using the cross detector no modulation click is audible. For example: The selection is enabled at t1, the microcontroller sets the zero cross bit (ZCM = 1) and then the mute bit (GMU = 1) via the I2C-bus. The output signal
TEA6320
follows the input A signal, until the next zero crossing occurs and then activates mute. After a fixed delay time at t2, the microcontroller sends the bits for input switching and mute inactive. The output signal remains muted until the next signal zero crossing of input B (IBL) occurs, and then follows that signal. The delay time t2 - t1 is e.g. 40 ms. Therefore the capacity Cm = 3.3 nF. The zero cross function is working at the lowest frequency of 40 Hz determined by the Cm capacitor.
handbook, full pagewidth
V 4 3 2 1 0 -1 -2 -3 -4
(2) (1)
MED436
t1
t2
(3)
t
(1) Input A (IAL). (2) Output. (3) Input B (IBL).
Fig.16 Zero cross function; only one channel shown.
1995 Dec 19
28
Philips Semiconductors
Preliminary specification
Sound fader control circuit
Loudness filter calculation example Figure 17 shows the basic loudness circuit with an external low-pass filter application. R1 allows an attenuation range of 21 dB while the boost is determined by the gain stage V2. Both result in a loudness control range of +20 to -12 dB. Defining fref as the frequency where the level does not change while switching loudness on/off. The external resistor R3 for fref can be calculated as: 10 R3 = R1 -------------------- . With Gv = -21 dB and R1 = 33 k, G 1 - 10 R3 = 3.2 k is generated. For the low-pass filter characteristic the value of the external capacitor C1 can be determined by setting a specific boost for a defined frequency and referring the gain to Gv at fref as indicated above. ( R1 + R3 ) x 10 - R3 1 -------------------- = ------------------------------------------------------------Gv j ( C1 ) -----20 1 - 10 For example: 3 dB boost at f = 1 kHz Gv = Gv(ref) + 3 dB = -18 dB; f = 1 kHz and C1 = 100 nF. If a loudness characteristic with additional high frequency boost is desired, an additional high-pass section has to be included in the external filter circuit as indicated in the block diagram. A filter configuration that provides AC coupling avoids offset voltage problems.
Gv -----20 -----20
v
TEA6320
handbook, halfpage
CKVL
0 dB 8 V1 R1 33 k 9
V2
Gv -----20
C1 R3
R2
MED437
Fig.17 Basic loudness circuit.
1995 Dec 19
29
Philips Semiconductors
Preliminary specification
Sound fader control circuit
INTERNAL PIN CONFIGURATIONS Values shown in Figs 18 to 30 are typical DC values; VCC = 8.5 V.
TEA6320
3 + 1 5V 1.8 k 4.25 V
80
MBE900
MBE901
Fig.18 Pin 1: SDA (I2C-bus data).
Fig.19 Pins 3, 4, 29, 30: output signals.
5 4.25 V + +
+
6 4.25 V
80 2.4 k
MBE902 MBE903
Fig.20 Pins 5 and 28: treble control capacitors.
Fig.21 Pins 6 and 27: bass control capacitor outputs.
1995 Dec 19
30
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
7 4.25 V 4.16 k + 8 4.25 V +
9.4 k 150 k
4.25 V 4.25 V
MED438 MBE904
Fig.22 Pins 7 and 26: bass control capacitor inputs.
Fig.23 Pins 8 and 25: input volume 1, control part.
9
+ 4.25 V +
10 4.25 V
80 1.12 k
MBE905
MBE906
Fig.24 Pins 9 and 24: input loudness, control part.
Fig.25 Pins 10 and 23: output source selector.
1995 Dec 19
31
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
12 11 4.25 V 1.3 k + + 8.5 V constant 2.2 V
maximum 200A 35 k 4.25 V
MBE907
0.6 A constant
4.5 k
MBE908
Fig.26 Pins 11, 13 to 18, 20, 22: inputs.
Fig.27 Pin 12: mute control.
+ 8.4 V 4.7 k 300 + 3.4 k 5 k 4.25 V 21 3.4 k
19
MHA063
Fig.28 Pin 19: filtering for supply; pin 21: reference voltage.
31
apply +8.5 V to this pin
32 5V 1.8 k
MBE909
MED440
Fig.29 Pin 31: supply voltage.
Fig.30 Pin 32: SCL (I2C-bus clock).
1995 Dec 19
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Philips Semiconductors
Preliminary specification
Sound fader control circuit
PACKAGE OUTLINES SDIP32: plastic shrink dual in-line package; 32 leads (400 mil)
TEA6320
SOT232-1
D seating plane
ME
A2 A
L
A1 c Z e b 32 17 b1 wM (e 1) MH
pin 1 index E
1
16
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 4.7 A1 min. 0.51 A2 max. 3.8 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 29.4 28.5 E (1) 9.1 8.7 e 1.778 e1 10.16 L 3.2 2.8 ME 10.7 10.2 MH 12.2 10.5 w 0.18 Z (1) max. 1.6
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT232-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-04
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Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
SO32: plastic small outline package; 32 leads; body width 7.5 mm
SOT287-1
D
E
A X
c y HE vM A
Z 32 17
Q A2 A1 pin 1 index Lp 1 e bp 16 wM L detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 0.02 0.01 c 0.27 0.18 0.011 0.007 D (1) 20.7 20.3 0.81 0.80 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 0.419 0.394 L 1.4 0.055 Lp 1.1 0.4 0.043 0.016 Q 1.2 1.0 0.047 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.95 0.55 0.037 0.022
0.012 0.096 0.004 0.086
8o 0o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT287-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-01-25 97-05-22
1995 Dec 19
34
Philips Semiconductors
Preliminary specification
Sound fader control circuit
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). SDIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
TEA6320
Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. WAVE SOLDERING Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1995 Dec 19
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Philips Semiconductors
Preliminary specification
Sound fader control circuit
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TEA6320
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1995 Dec 19
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Philips Semiconductors
Preliminary specification
Sound fader control circuit
NOTES
TEA6320
1995 Dec 19
37
Philips Semiconductors
Preliminary specification
Sound fader control circuit
NOTES
TEA6320
1995 Dec 19
38
Philips Semiconductors
Preliminary specification
Sound fader control circuit
NOTES
TEA6320
1995 Dec 19
39
Philips Semiconductors - a worldwide company
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Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-2724825 SCDS47 (c) Philips Electronics N.V. 1995
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
513061/1100/02/pp40 Document order number: Date of release: 1995 Dec 19 9397 750 00533

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